ID 59703
Title Transcription
タソウ ハイセン LSI ノ ダンセン コショウ ケンサ ニ カンスル ケンキュウ
Title Alternative
On testing of open faults in multi-layered wiring LSIs
Author
Yotsuyanagi, Hiroyuki Department of Information Solution, Institute of Technology and Science, Graduate School of the University of Tokushima Tokushima University Educator and Researcher Directory KAKEN Search Researchers
Hashizume, Masaki Department of Information Solution, Institute of Technology and Science, Graduate School of the University of Tokushima Tokushima University Educator and Researcher Directory KAKEN Search Researchers
Keywords
testing
open faults
VLSI
multi-layered wiring
adjacent lines
Content Type
Departmental Bulletin Paper
Description
Open faults are difficult to test since the floating wire occurred by an open fault has unstable
voltage. In this work, the effect of adjacent lines around an open fault in multi-layered wiring LSIs
is discussed. To observe the relation between an open fault and the adjacent lines, a 0.35μm CMOS
IC is designed and fabricated. The open fault macros with a transmission gate and with an
intentional break are included in the IC. The adjacent lines in the same layer and the different layers
are placed in the test chip. The simulation and experimental results show that the voltage at the
floating wire is affected by the adjacent lines.
Journal Title
徳島大学大学院ソシオテクノサイエンス研究部研究報告
ISSN
21859094
NCID
AA12214889
Volume
53
Start Page
16
End Page
20
Sort Key
16
Published Date
2008-05-30
EDB ID
FullText File
language
jpn
departments
Science and Technology