ディレイテスト可能なバウンダリスキャン設計手法

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Use this link to cite this item : https://repo.lib.tokushima-u.ac.jp/119658

ID	119658
Title Alternative	Delay Testable Design Using Modified Boundary Scan
Author	Yotsuyanagi, Hiroyuki Tokushima University Tokushima University Educator and Researcher Directory KAKEN Search Researchers Hashizume, Masaki Tokushima University Tokushima University Educator and Researcher Directory KAKEN Search Researchers
Content Type	Journal Article
Journal Title	Journal of The Japan Institute of Electronics Packaging
ISSN	13439677 1884121X
NCID	AA11231565
Publisher	エレクトロニクス実装学会
Volume	24
Issue	7
Start Page	663
End Page	667
Published Date	2021-11-01
EDB ID	384082
DOI (Published Version)	10.5104/jiep.24.663
URL ( Publisher's Version )	https://doi.org/10.5104/jiep.24.663
FullText File	jiep_24_7_663.pdf 916 KB
language	jpn
TextVersion	Publisher
departments	Science and Technology