| ID | 59703 |
| タイトルヨミ | タソウ ハイセン LSI ノ ダンセン コショウ ケンサ ニ カンスル ケンキュウ
|
| タイトル別表記 | On testing of open faults in multi-layered wiring LSIs
|
| 著者 | |
| キーワード | testing
open faults
VLSI
multi-layered wiring
adjacent lines
|
| 資料タイプ |
紀要論文
|
| 抄録 | Open faults are difficult to test since the floating wire occurred by an open fault has unstable
voltage. In this work, the effect of adjacent lines around an open fault in multi-layered wiring LSIs is discussed. To observe the relation between an open fault and the adjacent lines, a 0.35μm CMOS IC is designed and fabricated. The open fault macros with a transmission gate and with an intentional break are included in the IC. The adjacent lines in the same layer and the different layers are placed in the test chip. The simulation and experimental results show that the voltage at the floating wire is affected by the adjacent lines. |
| 掲載誌名 |
徳島大学大学院ソシオテクノサイエンス研究部研究報告
|
| ISSN | 21859094
|
| cat書誌ID | AA12214889
|
| 巻 | 53
|
| 開始ページ | 16
|
| 終了ページ | 20
|
| 並び順 | 16
|
| 発行日 | 2008-05-30
|
| EDB ID | |
| フルテキストファイル | |
| 言語 |
jpn
|
| 部局 |
理工学系
|
