多層配線LSIの断線故障検査に関する研究

Open faults are difficult to test since the floating wire occurred by an open fault has unstable
voltage. In this work, the effect of adjacent lines around an open fault in multi-layered wiring LSIs
is discussed. To observe the relation between an open fault and the adjacent lines, a 0.35μm CMOS
IC is designed and fabricated. The open fault macros with a transmission gate and with an
intentional break are included in the IC. The adjacent lines in the same layer and the different layers
are placed in the test chip. The simulation and experimental results show that the voltage at the
floating wire is affected by the adjacent lines.