112 Gb/s PAM-4 Silicon Photonics Receiver Integrated With SiGe-BiCMOS Linear TIA

We have developed a silicon photonics receiver integrated with a SiGe-BiCMOS linear transimpedance amplifier (TIA) using the flip-chip bonding technology to assist in resolving the I/O bottleneck problem in inter-chip data communication. The proposed device demonstrated optical 112 Gb/s four-level pulse amplitude modulation (PAM-4) operations and clear eye openings without any equalization for the pseudorandom binary sequence 215 – 1 signal. The 3 dB bandwidth and transimpedance gain were designed to be 37.1 GHz and 60.1 dBΩ, respectively, at a supply voltage of 3.3 V. The consumption current of the linear TIA was 95.1 mA, and it resulted in a power consumption of 314 mW (2.8 pJ/bit). A linear TIA circuit is a key technology for PAM-4 operation; therefore, we discussed the linearity of our receiver response through eye diagrams and simulation. The measured eye diagrams agreed with the simulation results, and the proposed device maintained a linear response for up to 450 μAp-p input current. In addition, its operation rate of 112 Gb/s is the highest operation rate reported for a silicon photonics PAM-4 receiver based on flip-chip 3D integration with a germanium photodetector and a SiGe-BiCMOS linear TIA.

論文本文は2024-01-20以降公開予定

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